1. Field of the Invention
The present invention relates to a TFT structure or a semiconductor integrated circuit construction having TFTs and to a method of fabricating such a structure. Especially, the invention relates to conductive interconnects for TFTs or for a semiconductor integrated circuit having TFTs Also, the invention relates to a method of forming such interconnects.
2. Description of the Related Art
Techniques for using TFTs (thin-film transistors) in an integrated circuit such as an active matrix liquid crystal display or image sensor fabricated on a glass substrate have been well known. Making reliable contacts of the semiconductor regions (such as source and drain) of the TFTs with conductive interconnects is important for such an integrated circuit. Also, decreasing the resistivity of the circuit is important. These requirements become more important and technical difficulties arise as the circuit device density increases.
The former requirement is associated with the fact that the used semiconductor thin film is quite thin. Generally, a semiconductor thin film is required to have good characteristics. However, it is quite difficult to form contacts on a semiconductor thin film as thin as hundreds of Angstroms. During fabrication of contact holes, overetching is highly likely to occur, forming holes or pits in the semiconductor holes. This phenomenon takes place, because the etch rates of silicon oxide and silicon nitride generally used as interlayer dielectrics and the etch rate of silicon (especially, in the case of dry etching) used as a semiconductor thin film are not very high.
With respect to the latter requirement, many resistors are made of thin films of semiconductors. Decreasing the semiconductor thin film portions, of the circuit is a fruitful countermeasure. However, the problem cannot be solved simply by devising the circuit arrangement because of design rule problems.
A method for solving the latter problem has been proposed. This method consists of siliciding almost all portions corresponding to the source and drain of each TFT. An example of this proposed method is next described by referring to FIGS. 2(A)-2(F).
A semiconductor film, or an active layer, 22 is formed on a substrate 21. A gate insulator layer 23 is formed over this semiconductor film 22. Then, a gate electrode 24 and a gate interconnect 25 are formed on the insulator layer. The gate electrode 24 and the gate interconnect 25 are in the, same layer. That is, they are fabricated at the same times Doped regions such as a source 26 and a drain 27 are formed in the active layer 22 (FIG. 2(A)).
Thereafter, a sidewall dielectric 28 is deposited on the sidewalls of the gate electrode 24 and of the gate interconnect 25 by a well-known anisotropic etching technique. This is normally accomplished by coating the whole surface with an insulator and then performing anisotropic etching. At this time, the gate insulator layer 23 is also etched, exposing the surface of the active layer.
A gate insulator film island 23a is formed under the gate electrode 24. Also, a gate insulator film island 23b is formed under the gate interconnect 25 (FIG. 2(B)).
Then, a metallization layer 29 is deposited over the whole surface (FIG. 2(C)). The metallization layer 29 and the active layer 22 are made to react with each other at their interface by thermal annealing, rapid thermal annealing, photo-annealing, or other means, thus obtaining a silicide layer, 30 and 31. The reaction may be made to progress to such an extent that the silicide layer reaches the bottom of the active layer as shown. Alternatively, the reaction may be stopped before the silicide layer reaches the bottom. In either case, the reaction starts from the interface between the metallization layer 29 and the active layer 22 and so the source and drain under the sidewall 28 remain semiconductive in nature (FIG. 2(D)).
Subsequently, the unreacted metallization layer portions are fully removed (FIG. 2(E)). Finally, a top layer of interconnect metal, 34 and 35, is formed on the interlayer dielectric 33 by a well-known, multi-level metallization technique. The top layer of interconnect metal forms contacts, 32a and 32b together with the silicide layer, 30 and 31. Also, the top layer of interconnect metal forms a contact 32c together with the gate interconnect 25.
In the example already described in conjunction with FIGS. 2(A)-2(E), anisotropically etched sidewalls are used. Techniques for anodizing gate electrodes, as disclosed in Japanese Patent Unexamined Publication Nos. 169974/1995, 169975/1995, and 218932/1995 may also be employed.
With this method, the resistivity of the circuit portions including TFTs can be reduced, because silicides have lower resistivities than semiconductor materials.
However, the problems produced where contact holes are created can be hardly solved, because the etch rates of silicides and silicon oxide or silicon nitride are not sufficiently high where a dry etching method is used. It is known that the method of using an interlayer dielectric film of silicon nitride for TFTs is advantageous, as described in Japanese Patent Unexamined Publication No. 326768/1995. With this method, if the etch rates of silicon nitride and the active layer are not sufficiently high where the interlayer dielectric is etched, it is difficult to detect the end point of the etching, since the silicon nitride layer is approximately 10 times as thick as the active layer.
Other problems may arise, depending on circuits. For example, in the structure shown in FIGS. 2(A)-2(F), the drain 27 or silicide 31 must gain access to the gate interconnect 25 via the top layer of interconnect metal 35, i.e., via two contacts. Contacts tend to produce many defects and have large resistivities. Obviously, the number of the contacts included in the circuit should be reduced to a minimum. Furthermore, the silicide layer is very thin, producing many defects at the contacts, though the possibility of overetching decreases. Consequently, the contact holes are required to have sufficient spread, which is an obstacle in achieving higher circuit density.